1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can perform a read operation and a write operation at a same time using a single port memory cell.
2. Description of the Related Art
With increase of functions of a semiconductor integrated circuit, the memory capacity of a memory circuit tends to increase. As such a memory circuit, a random access memory is known, in which a write operation is performed by use of a 1-system input and a read operation is performed by use of a 2-system output. In the random access memory, 2 systems are asynchronously operated regardless of competition in case of the read operation, and arbitration is performed based on an address data in case of the write operation. The memory circuit needs a special RAM section for the structure. Therefore, the memory needs transistors several times more than a single port-type RAM section having 1-system input/output.
A dual port RAM circuit is described in Japanese Laid Open Patent Application (JP-A-Heisei 6-161870) in which the increase of elements to be used can be avoided. Because this dual port RAM circuit uses a usual single port type RAM section, it is possible to be realized by generally used semi-customed ICs so that the cost can be reduced.
The technique in which a dual port RAM is apparently configured by using a single port RAM is known in Japanese Laid Open Patent Application (JP-A-Heisei 7-84987). This technique is characterized in that a delay circuit is used for arbitration when a write operation and a read operation compete with each other. The arbitration technique in which when a plurality of requests compete in this way, one request is performed while the other requests are waited is known in Japanese Laid Open Patent Application (JP-A-Heisei 8-328941).
The increase of the memory capacity of the memory circuit causes another problem in that the area of the memory circuit increases.
Next, referring to FIGS. 1 and 2, the problem on the area increase in an SRAM circuit as the memory circuit will be described.
Generally, when a read operation and a write operation are performed in a same cycle, a 2-port SRAM circuit is used. FIG. 1 shows a block diagram illustrating a circuit structure of the synchronous type 2-port SRAM circuit having a 8-column structure of n words.times.m bits. In the SRAM circuit shown in FIG. 1 is composed of two sets of word lines WLa [0:2.sup.n-2 -1] and WLb [0:2.sup.n-2 -1], and bit line pairs Da and DBa [0:7], and Db and DBb [0:7]. Therefore, the SRAM circuit is further composed of two sets of word line decoders 403a and 403b to select one of the two sets of word lines, and two sets of column selectors 406a and 406b.
One word line WLa [0:2.sup.n-2 -1] is selected by the word line decoder 403a based on (n-2) continuous ones of (n+1) address signals [0:n] of an address A inputted to an address latch A 402a and is driven by a word line driver A 404a. One word line WLb [0:2.sup.n-2 -1is selected by a word line decoder 403b based on (n-2) continuous ones of (n+1) address signals [0:n] of an address B inputted to an address latch B 402b and is driven by a word line driver B 404b. The bit line pair Da [0:7] and DBa [0:7] is selected by a column decoder A 405 and a column selector A 406a based on three continuous ones of the (n+1) address signals [0:n] of the address A inputted to the address latch A 402a and is connected to a sense amplifier A 407a and a write buffer A 408a. The bit line pair Db [0:7] and DBb [0:7] is selected by a column decoder B 405b and a column selector B 406b based on three continuous ones of the (N+1) address signals [0:2] of the address B inputted to an address latch B 402b and is connected to s sense amplifier B 407b and a write buffer B 408b. In this way, the 2-port SRAM circuit needs two sets of word lines and two sets of word line decoder and word line driver must be provided to select and to drive the respective word lines.
FIG. 2 is a diagram illustrating a memory cell 401 connected to two sets of word line and bit line pair in the SRAM circuit shown in FIG. 1. The 2-port SRAM memory cell 401 is composed of two inverter gates 411 and 412 and four transfer gates 413, 414, 415 and 416 in a latch section.
FIGS. 3A to 3S are timing charts of various signals in time periods T1 to T4.
In this way, the memory cell 401 shown in FIG. 2 needs further two transistors, compared with a usual single port memory cell 101. Thus, the chip area of the 2-port SRAM circuit increases compared with the single port SRAM circuit.
As described above, it is demanded that an operation mode of the 2-port SRAM circuit can be realized by use of an SRAM circuit using single port memory cells so that both of increase of the number of elements and increase of the chip area can be avoided.